To save precious layout space or increase interconnect efficiency, multiple chips of integrated circuits (ICs) can be stacked together as a single IC package. To that end, a three-dimensional (3D) stack packaging technology is used to package the chips of integrated circuits. Through-silicon vias (TSVs) are widely used to accomplish the 3D stack packaging technology. A through-silicon via is a vertical conductive via completely passing through a silicon wafer, a silicon board, a substrate of any material or die. Nowadays, a 3D integrated circuit (3D IC) is applied to a lot of fields such as memory stacks, image sensors or the like.
Although through-silicon vias come with many advantages, they also bring some issues into integrated circuits. For example, their gigantic size (hundred times bigger than traditional transistors) compared to their neighbors such as transistors, interconnects etc. would waste a lot of layout space. The more space they waste, the bigger a chip will be. Nowadays, all the electronic devices are expected to be small so wasting space is definitely not a smart idea. Therefore, there is a need to regain some spaces taken up by the through-silicon vias.